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w48s87-72 desktop/notebook frequency generator july 1999 ic works 101 nicholson lane san jose, ca 95134-1359 (408) 922-0202 revision 0.8 current information is available at www.icworks.com preliminary features ? maximized emi suppression using ic works? spread spectrum technology ? 0.5%spread spectrum clocking ? equivalent to the w48s67-72 with spread spectrum for tilamook, mmo and deschutes processors ? generates system clocks for cpu, ioapic, sdram, pci, usb plus 14.318mhz (ref0:1) ? serial data interface (sdata, sclock inputs) provides additional cpu/pci clock frequency selections, individual output clock disabling and other functions ? mode input pin selects optional power management input control pins (reconfigures pins 26 and 27) ? two fixed outputs separately selectable as 24mhz or 48mhz (default = 48mhz) ? vddq3 = 3.3v 5%, vddq2 = 2.5v5% ? uses external 14.318mhz crystal ? available in 48-pin ssop (300 mils) ? 10 w cpu output impedance figure 1 block diagram table 1 pin selectable frequency (note) note: additional frequency selections provided by serial data interface; refer to table5 on page9. figure 2 pin diagram table 2 order information vddq3 ref0 vddq2 ioapic cpu0 cpu1 cpu2 cpu3 sdram0 sdram1 sdram2 sdram3 sdram4 sdram5 sdram6 sdram7 pci_f pci0 xtal pll ref freq pll 1 60/66_sel mode x2 x1 ref1 vddq3 stop output control stop output control pci1 pwr_dwn# power down control pci2 pci3 pci4 pci5 48/24mhz 48/24mhz pll2 2 osc i/o control vddq2 cpu_stop# 60/66_sel cpu, sdram clocks (mhz) pci clocks (mhz) 0 60 30 1 66.8 33.4 part number freq. mask code package w48s87 72 h = ssop (300 mils) x = tssop ref1 ref0 gnd x1 x2 mode vddq3 pci_f pci0 gnd pci1 pci2 pci3 pci4 vddq3 pci5 gnd 60/66_sel sdata sclock vddq3 48/24mhz 48/24mhz gnd w 4 8 s 8 7 - 7 2 vddq3 cpu2.5# vddq2 ioapic pwr_dwn# gnd cpu0 cpu1 vddq2 cpu2 cpu3 gnd sdram0 sdram1 vddq3 sdram2 sdram3 gnd sdram4 sdram5 vddq3 sdram6/cpu_stop# sdram7/pci_stop# vddq3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
preliminary w48s87-72 page 2 desktop/notebook frequency generator revision 0.8 pin name pin no. pin type pin description cpu0:2 52,51,49 o cpu outputs 0 through 3: these four cpu outputs are controlled by the cpu_stop# control pin. output voltage swing is controlled by voltage applied to vddq2. pci0:5 9, 11, 12, 13, 14, 16 o pci bus outputs 0 through 5: these six pci outputs are controlled by the pci_stop# control pin. output voltage swing is controlled by voltage applied to vddq3. pci_f 8 o free running pci output: unlike pci0:5 outputs, this output is not con- trolled by the pci_stop# control pin. output voltage swing is controlled by voltage applied to vddq3. sdram0:5 36, 35, 33, 32, 30, 29 o sdram clock outputs 0 through 5: these six sdram clock outputs run synchronous to the cpu clock outputs. output voltage swing is controlled by voltage applied to vddq3. sdram6/ cpu_stop# 27 i/o sdram clock output 6 or cpu clock output stop control: this pin has dual functions, selectable by the mode input pin. when mode = 0, this pin becomes the cpu_stop# input. when mode = 1, this pin becomes sdram clock output 6. regarding use as a cpu_stop# input: when brought low, clock outputs cpu0:3 are stopped low after completing a full clock cycle (2-3 cpu clock latency). when brought high, clock outputs cpu0:3 are started beginning with a full clock cycle (2-3 cpu clock latency). regarding use as a sdram clock: output voltage swing is controlled by volt- age applied to vddq3. sdram7/ pci_stop# 26 i/o sdram clock output 7 or pci clock output stop control: this pin has dual functions, selectable by the mode input pin. when mode = 0, this pin becomes the pci_stop# input. when mode = 1, this pin becomes sdram clock output 7. pci_stop# input: when brought low, clock outputs pci0:5 are stopped low after completing a full clock cycle. when brought high, clock outputs pci0:5 are started beginning with a full clock cycle. clock latency provides one pci_f rising edge of pci clock following pci_stop# state change. regarding use as a sdram clock: output voltage swing is controlled by volt- age applied to vddq3. ioapic 45 o i/o apic clock output: provides 14.318mhz fixed frequency. the output voltage swing is controlled by vddq2. 48/24mhz 22, 23 o 48mhz / 24mhz output: fixed clock outputs that default to 48mhz following device power-up. either or both can be changed to 24mhz through use of the serial data interface (byte 0, bits 2 and 3). output voltage swing is controlled by voltage applied to vddq3 ref0:1 2, 1 o fixed 14.318mhz outputs 0 through 1: used for various system applica- tions. output voltage swing is controlled by voltage applied to vddq3. ref0 is stronger than ref1 and should be used for driving isa slots. cpu_2.5# 47 i set to logic 0 for vddq2 = 2.5v (0 to 2.5v cpu output swing). 60/66_sel 18 i 60 or 66mhz input selection: selects power-up default cpu clock fre- quency as shown in table1 on page1 (also determines sdram and pci clock frequency selections). can be used to change cpu clock frequency while device is in operation if serial data port bits 0-2 of byte 7 are logic 1 (default power-up condition).
preliminary w48s87-72 desktop/notebook frequency generator page 3 revision 0.8 x1 4 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318mhz crystal connection or as an external reference frequency input. x2 5 i crystal connection: an input connection for an external 14.318mhz crystal. if using an external reference, this pin must be left unconnected. pwr_dwn# 44 i power down control: when this input is low, device goes into a low power standby condition. all outputs are actively held low while in power down. cpu, sdram and pci clock outputs are stopped low after completing a full clock cycle (2-4 cpu clock cycle latency). when brought high, cpu, sdram and pci outputs start with a full clock cycle at full operating frequency (3ms maximum latency). mode 6 i mode control: this input selects the function of device pin 26 (sdram7/ pci_stop#) and pin 27 (sdram6/cpu_stop#). refer to description for those pins. sdata 19 i/o serial data input: data input for serial data interface. refer to serial data interface section that follows. sclock 20 i serial clock input: clock input for serial data interface. refer to serial data interface section that follows. vddq3 7, 15, 21, 25 28, 34, 48 p power connection: power supply for pci0:5, ref0:1, and 48/24mhz out- put buffers. connected to 3.3v supply. vddq2 46, 40 p power connection: power supply for ioapic0, cpu0:3 output buffer. con- nected to 2.5v supply. gnd 3, 10, 17, 24, 31, 37, 43 g ground connection: connect all ground pins to the common system ground plane. pin name pin no. pin type pin description
preliminary w48s87-72 page 4 desktop/notebook frequency generator revision 0.8 spread spectrum clocking the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increas- ing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. this effect is depicted in figure 3. as shown in figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the fre- quency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 4. this waveform, as discussed in "spread spectrum clock generation for the reduction of radiated emissions" by bush, fessler, and hardin, produces the maximum reduc- tion in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is 0.5% of the center frequency. figure 6 details the ic works spreading pattern. ic works does offer options with more spread and greater emi reduction. contact your local sales representative for details on these devices. figure 3 clock harmonic with and without sscg modulation frequency domain representation spread spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1-0 in data byte 0 of the i 2 c data stream. refer to table 5 for more details. figure 4 typical modulation profile max (+.0.5%) min. (- 0 .5%) 1 0 % 2 0 % 3 0 % 4 0 % 5 0 % 6 0 % 7 0 % 8 0 % 9 0 % 1 0 0 % 1 0 % 2 0 % 3 0 % 4 0 % 5 0 % 6 0 % 7 0 % 8 0 % 9 0 % 1 0 0 % f r e q u e n c y
preliminary w48s87-72 desktop/notebook frequency generator page 5 revision 0.8 serial data interface the w48s87-72 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. upon power-up, the w48s87-72 initializes with default register settings, therefore the use of this serial data interface is optional. the serial interface is write-only (to the clock chip) and is the dedicated function of device pins sdata and sclock. in motherboard applica- tions, sdata and sclock are typically driven by two logic outputs of the chipset. clock device register changes are nor- mally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. table 3 summarizes the con- trol functions of the serial data interface. table 3 serial data interface control functions summary control function description common application clock output disable any individual clock output(s) can be disabled. disabled outputs are actively held low. unused outputs are disabled to reduce emi and system power. examples are clock out- puts to unused sdram dimm socket or pci slot. 48/24mhz clock output frequency selection 48/24mhz clock outputs can be set to 48mhz or 24mhz. provides flexibility in super i/o and usb device selection. cpu clock frequency selection provides cpu/pci frequency selections beyond the 60 and 66.6mhz selections that are provided by the sel60/66 input pin. frequency is changed in a smooth and controlled fashion. for alternate cpu devices, and power man- agement options. smooth frequency transi- tion allows cpu frequency change under normal system operation. output tristate puts all clock outputs into a high impedance state. production pcb testing. test mode all clock outputs toggle in relation with x1 input, internal pll is bypassed. refer to table 5. production pcb testing. (reserved) reserved function for future device revision or production device testing. no user application. register bit must be written as 0.
preliminary w48s87-72 page 6 desktop/notebook frequency generator revision 0.8 operation data is written to the w48s87-72 in eleven bytes of eight bits each. bytes are written in the order shown in table 4. table 4 byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the w48s87-72 to accept the bits in data bytes 0-7 for internal register configuration. since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the w48s87-72 is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code don?t care unused by the w48s87-72, therefore bit values are ignored (don?t care). this byte must be included in the data write sequence to main- tain proper byte allocation. the command code byte is part of the standard serial communication protocol and may be used when writ- ing to another addressed slave receiver on the serial data bus. 3 byte count don?t care unused by the w48s87-72, therefore bit values are ignored (don?t care). this byte must be included in the data write sequence to main- tain proper byte allocation. the byte count byte is part of the stan- dard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 data byte 0 refer to table 5 the data bits in data bytes 0-7 set internal w48s87-72 registers that control device operation. the data bits are only accepted when the address byte bit sequence is 11010010, as noted above. for descrip- tion of bit control functions, refer to table 5, data byte serial configu- ration map. 5 data byte 1 6 data byte 2 7 data byte 3 8 data byte 4 9 data byte 5 10 data byte 6 11 data byte 7
preliminary w48s87-72 desktop/notebook frequency generator page 7 revision 0.8 writing data bytes each bit in data bytes 0-7 control a particular device function except for the "reserved" bits which must be written as a logic 0. bits are written msb (most significant bit) first, which is bit 7. table 5 gives the bit formats for registers located in data bytes 0-7. table 5 details additional frequency selections that are avail- able through the serial data interface. table 6 details the select functions for byte 0, bits 1 and 0. bit(s) affected pin control function bit control default pin no. pin name 0 1 data byte 0 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- sel_4 refer to table 5 0 4 -- -- sel_3 refer to table 5 0 3 23 48/24mhz 48/24mhz clock output frequency selection 24mhz 48mhz 1 2 22 48/24mhz 48/24mhz clock output frequency selection 24mhz 48mhz 1 1-0 -- -- bit 1 bit 0 function (see table 6 for function details) 0 0 normal operation 0 1 test mode 1 0 spread spectrum on 1 1 all outputs tristated 00 data byte 1 7 23 48/24mhz clock output disable low active 1 6 22 48/24mhz clock output disable low active 1 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 38 cpu3 clock output disable low active 1 2 39 cpu2 clock output disable low active 1 1 41 cpu1 clock output disable low active 1 0 42 cpu0 clock output disable low active 1 data byte 2 7 -- -- (reserved) -- -- 0 6 8 pci_f clock output disable low active 1 5 16 pci5 clock output disable low active 1 4 14 pci4 clock output disable low active 1 3 13 pci3 clock output disable low active 1 2 12 pci2 clock output disable low active 1 1 11 pci1 clock output disable low active 1 0 9 pci0 clock output disable low active 1 data byte 3 7 26 sdram7 clock output disable low active 1 6 27 sdram6 clock output disable low active 1 5 29 sdram5 clock output disable low active 1 4 30 sdram4 clock output disable low active 1 3 32 sdram3 clock output disable low active 1
preliminary w48s87-72 page 8 desktop/notebook frequency generator revision 0.8 2 33 sdram2 clock output disable low active 1 1 35 sdram1 clock output disable low active 1 0 36 sdram0 clock output disable low active 1 data byte 4 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 -- -- (reserved) -- -- 0 data byte 5 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 45 ioapic clock output disable low active 1 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 1 ref1 clock output disable low active 1 0 2 ref0 clock output disable low active 1 data byte 6 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 -- -- (reserved) -- -- 0 data byte 7 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- sel_2 refer to table 5 1 1 -- -- sel_1 refer to table 5 1 0 -- -- sel_0 refer to table 5 1 bit(s) affected pin control function bit control default pin no. pin name 0 1
preliminary w48s87-72 desktop/notebook frequency generator page 9 revision 0.8 table 5 additional frequency selections through serial data interface data bytes note: power-up default values denoted by shading. 60/66_sel is set by the user. table 6 select function for data byte 0, bits 0:1 notes: 1. cpu, sdram and pci frequency selections are listed in table 1 and table 5. 2. in test mode, the 48/24mhz clock outputs are: - x1/2 if 48mhz is selected - x1/4 if 24mhz is selected date byte 0 60/66_sel (pin 18) date byte 7 cpu0:3 sdram0:7 pci_f pci0:5 spread spectrum% bit 5 sel_4 bit 4 sel_3 bit 2 sel_2 bit 1 sel_1 bit 0 sel_0 0 0 x 0 0 0 75.0 cpu/2 0.5 0 0 x 0 0 1 75.0 32 0.5 0 0 x 0 1 0 83.31 32 0.5 0 0 x 0 1 1 33.41 cpu/2 0.5 0 0 x 1 0 0 50.11 cpu/2 0.5 0 0 x 1 0 1 68.52 cpu/2 0.5 0 0 x 1 1 0 60.0 cpu/2 0.5 0 0 0 1 1 1 60.0 cpu/2 0.5 0 0 1 1 1 1 66.82 cpu/2 0.5 0 1 0 x x x 60.0 cpu/2 0.5 0 1 1 x x x 66.6 cpu/2 -0.5 1 0 0 x x x 60.0 cpu/2 0.5 1 0 1 x x x 66.6 cpu/2 -0.5 1 1 0 x x x 60.0 cpu/2 0.5 1 1 1 x x x 66.6 cpu/2 -0.5 function input conditions output conditions data byte 0 cpu0:3, sdram0:7 pci_f, pci0:5 ref0:2, ioapic 48/24mhz bit 1 bit 0 normal operation 0 0 note 1 note 1 14.318mhz 48 or 24mhz test mode 0 1 x1/2 x1/4 x1 note 2 spread spectrum on 1 0 note 1 note 1 14.318mhz 48 or 24mhz tristate 1 1 hi-z hi-z hi-z hi-z
preliminary w48s87-72 page 10 desktop/notebook frequency generator revision 0.8 how to use the serial data interface electrical requirements figure 5 illustrates electrical characteristics for the serial interface bus used with the w48s87-72. devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. the pull- up resistor on the bus (both clock and data lines) establish a default logic 1. all bus devices generally have logic inputs to receive data. although the w48s87-72 is a receive-only device (no data write-back capability), it does transmit an "acknowledge" data pulse after each byte is received. thus, the sdata line can both transmit and receive data. the pull-up resistor should be sized to meet the rise and fall times specified in ac parameters, taking into consideration total bus line capacitance. figure 5 serial interface bus electrical characteristics data in data out n clock in clock out chip set (serial bus master transmitter) sdclk sdata serial bus clock line serial bus data line n data in data out clock in clock device (serial bus slave receiver) sclock sdata n ~ 2k w ~ 2k w vdd vdd
preliminary w48s87-72 desktop/notebook frequency generator page 11 revision 0.8 signaling requirements as shown in figure 6, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock high (logic 1) pulse. a transitioning data line during a clock high pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). a write sequence is initiated by a "start bit" as shown in fig- ure 7. a "stop bit" signifies that a transmission has ended. as stated previously, the w48s87-72 sends an "acknowl- edge" pulse after receiving eight data bits in each byte as shown in figure 8. sending data to the w48s87-72 the device accepts data once it has detected a valid start bit and address byte sequence. device functionality is changed upon the receipt of each data bit (registers are not double buffered). partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). transmission is truncated with either a stop bit or new start bit (restart condition). figure 6 serial data bus valid data bit figure 7 serial data bus start and stop bit sdata sclock valid data bit change of data allowed sdata sclock start bit stop bit
preliminary w48s87-72 page 12 desktop/notebook frequency generator revision 0.8 figure 8 serial data bus write sequence figure 9 serial data bus timing diagram m s b 1 2 3 4 5 6 7 8 a 1 2 3 4 5 6 7 8 a 1 2 3 4 s c l o c k 1 2 3 4 5 6 7 8 a 1 1 0 1 0 0 1 0 l s b m s b m s b l s b s d a t a s d a t a s i g n a l i n g f r o m s y s t e m c o r e l o g i c s t a r t c o n d i t i o n m s b l s b s l a v e a d d r e s s ( f i r s t b y t e ) c o m m a n d c o d e ( s e c o n d b y t e ) l a s t d a t a b y t e ( l a s t b y t e ) b y t e c o u n t ( t h i r d b y t e ) s t o p c o n d i t i o n s i g n a l i n g b y c l o c k d e v i c e a c k n o w l e d g m e n t b i t f r o m c l o c k d e v i c e t s t h d t l o w t r t h i g h t f t d s u t d h d t s p t s p s u t s t h d t s p s u t s p f s d a t a s c l o c k
preliminary w48s87-72 desktop/notebook frequency generator page 13 revision 0.8 absolute maximum ratings stresses greater than those listed in this table may cause permanent damage to the device. these represent a stress rating only. operation of the device at these or any other con- ditions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. symbol parameter rating unit v dd , v in voltage on any pin with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c t b ambient temperature under bias ?55 to +125 c t a operating temperature 0 to +70 c esd prot input esd protection 2 (min) kv dc electrical characteristics: t a = 0c to +70c, v ddq3 = 3.3v5% (3.135-3.465v) f xtl = 14.31818mhz, v ddq2 = 2.55% symbol parameter min typ max unit test condition supply current i ddq3 supply current (3.3v) 120 150 200 ma cpuclk = 66.8mhz outputs loaded (note 1) i ddq2 supply current (2.5v) 50 ma cpuclk = 66.8mhz outputs loaded (note 1) logic inputs v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current (note 2) 10 a i ih input high current (note 2) 10 a clock outputs v ol output low voltage 50 mv i ol = 2ma v oh output high voltage 3.1 v i oh = ?1ma v oh output high voltage (cpu, ioapic) 2.2 v i oh = ?1ma i ol output low current: cpu0:3 155 ma v ol = 1.25v sdram0:7 100 ma v ol = 1.5v pci_f, pci0:5 95 ma v ol = 1.5v ioapic 85 ma v ol = 1.25v ref0 75 ma v ol = 1.5v ref1 60 ma v ol = 1.5v 48/24mhz 60 ma v ol = 1.5v
preliminary w48s87-72 page 14 desktop/notebook frequency generator revision 0.8 notes: 1. all clock outputs loaded with maximum lump capacitance test load specified in ac electrical characteristics section. 2. w48s87-72 logic inputs have internal pull-up devices. (not cmos level) 3. x1 input threshold voltage (typical) is v ddq3 /2. 4. the w48s87-72 contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. total load placed on crystal is 14pf; this includes typical stray capacitance of short pcb traces to crystal. 5. x1 input capacitance is applicable when driving x1 with an external clock source (x2 is left unconnected). i oh output high current: cpu0:3 125 ma v oh = 1.25v sdram0:7 95 ma v oh = 1.5v pci_f, pci0:5 100 ma v oh = 1.5v ioapic 80 ma v oh = 1.25v ref0 80 ma v oh = 1.5v ref1 65 ma v oh = 1.5v 48/24mhz 60 ma v oh = 1.5v crystal oscillator v th x1 input threshold voltage (note 3) 1.65 v v dd = 3.3v c load load capacitance, imposed on external crystal (note 4) 14 pf c in,x1 x1 input capacitance (note 5) 28 pf pin x2 unconnected pin capacitance/inductance c in input pin capacitance 5 pf except x1 and x2 c out output pin capacitance 6 pf l in input pin inductance 7 nh serial input port v il input low voltage 0.4 0.3v dd v v dd = 3.3v v ih input high voltage 0.7v dd 2.4 v v dd = 3.3v i il input low current 10 10 a no internal pull-up/down on sclock i ih input high current 10 10 a no internal pull-up/down on sclock i ol sink current into sdata or sclock, open drain n-channel device on 5 10 15 ma i ol = 0.3v dd c in input capacitance of sdata and sclock 5 10 pf c sdata total capacitance of sdata bus -- -- 400 pf c sclock total capacitance of sclock bus -- -- 400 pf dc electrical characteristics: (cont.) t a = 0c to +70c, v ddq3 = 3.3v5% (3.135-3.465v) f xtl = 14.31818mhz, v ddq2 = 2.55% symbol parameter min typ max unit test condition
preliminary w48s87-72 desktop/notebook frequency generator page 15 revision 0.8 ac electrical characteristics: t a = 0c to +70c, v dd = v ddq3 = 3.3v5% (3.135-3.465v) f xtl = 14.31818mhz, v ddq2 = 2.55% ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. cpu clock outputs, cpu0:3 (lump capacitance test load = 20pf) symbol parameter cpu = 66.8mhz cpu = 60mhz unit test condition/comments min typ max min typ max t p period 15 16.7 ns measured on rising edge at 1.5v. f frequency, actual 66.8 59.876 mhz determined by pll divider ratio. t h high time 5.2 6 ns duration of clock cycle above 2.4v. t l low time 5 5.8 ns duration of clock cycle below 0.4v. t r output rise edge rate 1 4 1 1 v/ns measured from 0.4v to 2.4v. t f output fall edge rate 1 4 1 4 v/ns measured from 2.4v to 0.4v. t d duty cycle 45 52 55 45 52 55 % measured on rising and falling edge at 1.25v. t jc jitter, cycle-to-cycle 250 250 ps measured on rising edge at 1.25v. maximum difference of cycle time between two adjacent cycles. t sk output skew 250 250 ps measured on rising edge at 1.25v. f st frequency stabilization from power-up (cold start) 3 3 ms assumes full supply voltage reached within 1ms from power-up. short cycles exist prior to frequency stabilization. z o ac output impedance 10 10 ohm average value during switching transition. used for determining series termination value. sdram clock outputs, sdram0:7 (lump capacitance test load = 30pf) symbol parameter cpu = 66.8mhz cpu = 60mhz unit test condition/comments min typ max min typ max t p period 15 16.7 ns measured on rising edge at 1.5v. f frequency, actual 66.8 59.876 mhz determined by pll divider ratio. t r output rise edge rate 1 4 1 4 v/ns measured from 0.4v to 2.4v. t f output fall edge rate 1 4 1 v/ns measured from 2.4v to 0.4v. t d duty cycle 45 50 55 45 50 55 % measured on rising and falling edge at 1.5v. t jc jitter, cycle-to-cycle 250 250 ps measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. t sk output skew 100 100 ps measured on rising edge at 1.5v. t sk cpu to sdram clock skew 500 500 ps covers all cpu/sdram outputs. measured on rising edge at 1.5v. f st frequency stabilization from power-up (cold start) 3 3 ms assumes full supply voltage reached within 1ms from power-up. short cycles exist prior to frequency stabilization. z o ac output impedance 16 16 ohm average value during switching transition. used for determining series termination value.
preliminary w48s87-72 page 16 desktop/notebook frequency generator revision 0.8 pci clock outputs, pci0:5 (lump capacitance test load = 30pf) symbol parameter cpu = 66.8mhz cpu = 60mhz unit test condition/comments min typ max min typ max t p period 30 33.3 ns measured on rising edge at 1.5v. f frequency, actual 33.4 29.938 mhz determined by pll divider ratio. t h high time 12 13.3 ns duration of clock cycle above 2.4v. t l low time 12 13.3 ns duration of clock cycle below 0.4v. t r output rise edge rate 1 4 1 4 v/ns t f output fall edge rate 1 4 1 4 v/ns t d duty cycle 45 51 55 45 51 55 % measured on rising and falling edge at 1.5v. t jc jitter, cycle-to-cycle 250 250 ps measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. t sk output skew 250 250 ps measured on rising edge at 1.5v. t o cpu to pci clock offset 1 4 1 4 ns covers all cpu/pci outputs. measured on rising edge at 1.5v. cpu leads pci output. f st frequency stabilization from power-up (cold start) 3 3 ms assumes full supply voltage reached within 1ms from power-up. short cycles exist prior to frequency stabilization. z o ac output impedance 30 30 ohm average value during switching transition. used for determining series termination value. i/o apic clock output (lump capacitance test load = 20pf) symbol parameter cpu = 60/66.8mhz unit test condition/comments min typ max f frequency, actual 14.31818 mhz frequency generated by crystal oscillator. t r output rise edge rate 1 4 v/ns t f output fall edge rate 1 4 v/ns t d duty cycle 45 52.5 55 % measured on rising and falling edge at 1.25v. f st frequency stabilization from power-up (cold start) 1.5 ms assumes full supply voltage reached within 1ms from power-up. short cycles exist prior to frequency stabilization. z o ac output impedance 15 ohm average value during switching transition. used for determining series termination value. ac electrical characteristics (cont)
preliminary w48s87-72 desktop/notebook frequency generator page 17 revision 0.8 ref0 clock output (lump capacitance test load = 45pf) symbol parameter cpu = 60/66.8mhz unit test condition/comments min typ max f frequency, actual 14.31818 mhz frequency generated by crystal oscillator. t r output rise edge rate 1 4 v/ns measured from 0.4v to 2.4v. t f output fall edge rate 1 4 v/ns measured from 2.4v to 0.4v. t d duty cycle 45 50 55 % measured on rising and falling edge at 1.5v. f st frequency stabilization from power-up (cold start) 1.5 ms assumes full supply voltage reached within 1ms from power-up. short cycles exist prior to frequency stabilization. z o ac output impedance 16 ohm average value during switching transition. used for determining series termination value. ref1 clock output (lump capacitance test load = 20pf) symbol parameter cpu = 60/66.8mhz unit test condition/comments min typ max f frequency, actual 14.31818 mhz frequency generated by crystal oscillator. t r output rise edge rate 0.5 2 v/ns t f output fall edge rate 0.5 2 v/ns t d duty cycle 45 55 % measured on rising and falling edge at 1.5v. f st frequency stabilization from power-up (cold start) 1.5 ms assumes full supply voltage reached within 1ms from power-up. short cycles exist prior to frequency stabilization. z o ac output impedance 40 ohm average value during switching transition. used for determining series termination value. 48/24mhz clock output (lump capacitance test load = 20pf) symbol parameter cpu = 60/66.8mhz unit test condition/comments min typ max f frequency, actual 48.008/24.004 mhz determined by pll divider ratio (see n/m below). f d deviation from 48mhz +167 ppm (48.008 ? 48)/48 m/n pll ratio 57/17 (14.31818mhz x 57/17 = 48.008mhz) t r output rise edge rate 0.5 2 v/ns t f output fall edge rate 0.5 2 v/ns t d duty cycle 45 50 55 % measured on rising and falling edge at 1.5v. f st frequency stabilization from power-up (cold start) 3 ms assumes full supply voltage reached within 1ms from power-up. short cycles exist prior to fre- quency stabilization. z o ac output impedance 40 ohm average value during switching transition. used for determining series termination value. ac electrical characteristics (cont)
preliminary w48s87-72 page 18 desktop/notebook frequency generator revision 0.8 serial input port symbol parameter min typ max unit test condition f sclock sclock frequency 0 100 khz normal mode t sthd start hold time 4.0 s t low sclock low time 4.7 s t high sclock high time 4.0 s t dsu data setup time 250 ns t dhd data hold time 0 ns (transmitter should provide a 300ns hold time to ensure proper timing at the receiver.) t r rise time, sdata and sclock 1000 ns from 0.3v dd to 0.7v dd t f fall time, sdata and sclock 300 ns from 0.7v dd to 0.3v dd t stsu stop setup time 4.0 s t spf bus free time between stop and start condition 4.7 s t sp allowable noise spike pulse width 50 ns ac electrical characteristics (cont)
preliminary w48s87-72 desktop/notebook frequency generator page 19 revision 0.8 mechanical package outline figure 10 48-pin small shrink outline package (ssop, 300 mils) summary of nominal dimensions in inches: body width: .296 lead pitch: .025 body length: .625 body height: .102
preliminary w48s87-72 ic works 101 nicholson lanet san jose, ca 95134-1354 (408) 922-0202 ic works, inc. reserves the right to amend or discontinue this product without notice. cir- cuit and timing diagrams used the describe ic works product operations and applications are included as a means of illustrating a typical product application. complete information for design purposes is not necessarily given. this information has been carefully checked and is believed to be entirely reliable. ic works, however, will not assume any responsibil- ity for inaccuracies. life support applications: ic works products are not designed for use in life support applications, devices, or sys- tems where malfunctions of the ic works product can reasonably be expected to result in personal injury. ic works customers using or selling ic works products for use in such applications do so at their own risk and agree to fully indemnify ic works for any damages resulting in such improper use or sale. figure 11 48-pin thin shrink small outline package (tssop) mechanical package outline

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